Job Description

Do you love creating elegant solutions to sophisticated challenges? As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. In this job, you will be responsible for timing closure of highly complex GPU designs that go in every Apple product and will have amazing opportunities to set new standards for the next generation GPU designs. You will gain exposure to different aspects of product development, from concept to post silicon validation! You will collaborate with a variety of fields including Architecture, RTL, Synthesis, Clocking, DFT, Physical design and Post silicon engineering to ensure the best design practices are followed for a smooth timing convergence.

Description

- Interact with RTL, architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows. - Work with Synthesis and Physical Design teams to implement the best design optimized for power, performance and timing. - Setting up all DFT modes and making sure all test features are properly timed. - Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports. - Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure. - Run ECO flows on the design and responsible for close timing. - Drive and support tapeout activities by running a full suite of signoff checks to ensure a high quality silicon for manufacture. - Work with CAD and Vendors to constantly improve the flow and bring in groundbreaking features to the analysis flows.

Minimum Qualifications

Key Qualifications

• We are looking for candidates with 3+ years of hands-on experience in STA and timing closure, including:
• Familiar with STA concepts and good understanding of cross-talk, OCV, noise, etc.
• Experience with timing closure, analysis of large volume data, identifying and driving fixes, generating and providing ECOs for timing closure.
• General knowledge in one or more multi-functional areas like DFT, synthesis, PD, clocking is preferable.
• Be a strong teammate, good communicator and able to work with others driving timing closure and influencing the best design practices to improve efficiency.
• Have programming skills with TCL and Primetime APIs. Exposure to Python/Perl would be added advantage.

Preferred Qualifications

Education & Experience

We are looking for candidates with BS + 3 years of relevant experience.

Additional Requirements

• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

- Interact with RTL, architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows. - Work with Synthesis and Physical Design teams to implement the best design optimized for power, performance and timing. - Setting up all DFT modes and making sure all test features are properly timed. - Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports. - Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure. - Run ECO flows on the design and responsible for close timing. - Drive and support tapeout activities by running a full suite of signoff checks to ensure a high quality silicon for manufacture. - Work with CAD and Vendors to constantly improve the flow and bring in groundbreaking features to the analysis flows. We are looking for candidates with BS + 3 years of relevant experience.

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