We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a passionate and skilled Analog Design Engineer with a strong background in designing, developing, and evaluating physical IP such as SERDES, DDR, or Memory. You thrive in a dynamic environment and are eager to take on new challenges with minimal supervision. Your expertise in clocking, DCC, and deskew technologies is unparalleled, and you are well-versed in the full SOC Design Cycle with a focus on Physical Design. You possess a keen eye for detail and are committed to delivering high-quality results that drive innovation and success.
As an excellent communicator, you effectively collaborate with cross-functional teams and influence decision-making processes. You are adept at evaluating complex issues and providing innovative solutions that align with strategic goals. Your extensive knowledge and experience in analog design make you a valuable asset to our team, and you are motivated by the opportunity to contribute to cutting-edge technological advancements.
What You’ll Be Doing:
Designing, developing, and evaluating physical IP such as SERDES, DDR, and Memory.
Focusing on clocking, DCC, and deskew technologies to ensure optimal performance.
Collaborating with cross-functional teams to integrate and verify IP designs.
Conducting extensive simulations and analyses to validate design robustness.
Providing technical expertise and guidance to support product development and innovation.
Continuously improving design methodologies and processes to enhance efficiency and quality.
The Impact You Will Have:
Driving the development of high-performance physical IP that powers next-generation technologies.
Ensuring the reliability and efficiency of clocking, DCC, and deskew solutions in our products.
Contributing to the success of Synopsys' strategic goals through innovative design solutions.
Enhancing the capabilities of our products and platforms through expert technical insights.
Fostering a culture of continuous improvement and excellence within the engineering team.
Supporting the adoption and usability of our products by providing top-tier engineering expertise.
What You’ll Need:
Extensive experience in analog design, with a focus on physical IP such as SERDES, DDR, and Memory.
MS with 10+ years of direct industry experience.
Strong expertise in clocking, DCC, and deskew technologies.
Proficiency in the full SOC Design Cycle, with a focus on Physical Design.
Advanced simulation and analysis skills to validate design robustness.
Excellent problem-solving abilities and a keen eye for detail.
Who You Are:
A proactive and independent worker with minimal need for supervision.
An effective communicator with the ability to influence and collaborate with cross-functional teams.
A strategic thinker who can evaluate complex issues and provide innovative solutions.
A dedicated professional committed to continuous improvement and excellence.
A passionate engineer driven by the opportunity to contribute to cutting-edge technologies.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
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